NXP has unveiled the i.MX 952, a new addition to its i.MX 95 family of application processors. Designed for AI-driven automotive and industrial systems, the chip targets use cases such as driver monitoring, child presence detection, and human–machine interface (HMI) control in next-generation cockpits and intelligent machinery.
The i.MX 952 integrates up to four Arm Cortex-A55 application cores, along with Cortex-M7 and Cortex-M33 microcontroller cores for real-time and safety-critical workloads. It meets ASIL-B requirements under ISO 26262 and supports SIL2/SIL3 safety integrity levels. A built-in eIQ Neutron NPU enables efficient AI sensor fusion, while its 5-Gpixel/s image signal processor (ISP) supports RGB-IR imaging for low-light and infrared sensing.
Notably, the i.MX 952 is the first processor in the series to feature integrated local dimming control, allowing for improved display brightness management and energy efficiency — a key benefit for modern vehicle dashboards and industrial displays.
Security features include NXP’s EdgeLock Secure Enclave, with post-quantum cryptography (PQC) support, compliance with ISO 21434 for automotive cybersecurity, and IEC 62443 for industrial security. The processor also aligns with NXP’s PF09 PMIC, PF53 regulator, Trimension UWB, and IW693/AW693 Wi-Fi 6/6E SoCs, maintaining pin compatibility with the broader i.MX 95 platform.
NXP i.MX 952: AI Processor for Automotive and Industrial Applications
i.MX 952 Core Specifications
| Category | Specification |
|---|---|
| CPU (Central Processing Unit) | - Up to 4× Arm Cortex-A55 cores with 32KB+32KB L1 cache, 64KB L2 cache, and 512KB ECC-protected L3 cache - 1× Arm Cortex-M7 real-time core with 32KB+32KB cache and 512KB ECC-protected TCM - 1× Arm Cortex-M33 low-power security/system MCU with 16KB+16KB cache and 256KB ECC-protected on-chip SRAM |
| GPU (Graphics) | Unnamed Arm Mali 3D GPU with OpenGL ES 3.2, Vulkan 1.2, and OpenCL 3.0 support, plus integrated 2D GPU |
| AI Accelerator | NXP eIQ Neutron Neural Processing Unit (NPU) |
| Memory Interface | Up to 32-bit LPDDR5 (6000 MT/s) or LPDDR4X (4266 MT/s) with inline ECC and encryption; up to 768 KB ECC-protected on-chip OCRAM |
| Storage Interfaces | 3× uSDHC (SD 3.0 / SDIO 3.0 / eMMC 5.1); 8-bit/4-bit SPI Flash (with inline encryption, IPED, SPI NOR/NAND) |
| Display Interfaces | 1× 4-lane MIPI-DSI; 2× 4-lane or 1× 8-lane LVDS with integrated local dimming support |
| Camera Interfaces | 4-lane or 2×2-lane MIPI-CSI interfaces |
| Audio | 15-channel I²S TDM Tx/Rx, SPDIF Tx/Rx, and PDM microphone inputs |
| Networking | 1× 2.5 Gb Ethernet (TSN), 2× 1 Gb Ethernet (TSN, AVB, IEEE 1588, EEE) |
| USB | 2× USB 2.0 with integrated PHY |
| PCIe | 1× PCIe Gen 3.0 (1 lane, 2.5 Gbps multiplexer) |
| Serial Interfaces | 3× CAN-FD, 8× UART/USART |
| Other Peripherals | 8× LPI²C, 8× LPSPI, 2× I³C, and 2× 32-pin FlexIO interfaces (for camera, bus, or serial I/O) |
| Security (EdgeLock Secure Enclave) | - Secure boot, secure clock, crypto engine, tamper detection - eFuse key storage, hardware RNG, EdgeLock Prime accelerator - Post-Quantum Cryptography (PQC) support - Compliant with IEC 61508 (SIL 2) and ISO 26262 (ASIL B) |
| Packaging | 19 × 19 mm FCBGA (0.7 mm pitch); 15 × 15 mm FCBGA (0.5 mm pitch) |
| Temperature Ranges | - Consumer: 0 °C to 95 °C - Industrial: -40 °C to 105 °C - Automotive/Extended Industrial: -40 °C to 125 °C |
The i.MX 952 inherits the heterogeneous architecture of the i.MX 95 series — combining Cortex-A55, M7, and M33 cores, an eIQ Neutron NPU, and a high-throughput ISP. The key updates include:
- Integrated local dimming engine, improving display efficiency and contrast in automotive dashboards.
- Expanded EdgeLock Secure Enclave with Post-Quantum Cryptography support for future-proof security.
- Optimized architecture: reduced from 6 to 4 Cortex-A55 cores, streamlined on-chip memory, and simplified I/O (no USB 3.0 or 10 GbE), striking a balance between AI performance, functional safety, and power efficiency (up to SIL 3 support).
For software and development, NXP offers:
- Linux and Android BSPs for the Arm Cortex-A55 application cores.
- FreeRTOS support for the Cortex-M7 and M33 real-time/safety cores.
- eIQ Neutron SDK, enabling AI model training, quantization, and deployment for edge ML and vision workloads.
- Yocto-based Linux SDK, EdgeLock security framework, and MCUXpresso toolchain for secure boot configuration and multi-core integration across automotive, industrial, and IoT use cases.
Currently, the i.MX 952 is in a pre-production phase. Specifications may evolve before mass production, but its design clearly positions it as a cost-optimized, AI-capable SoC bridging the gap between traditional embedded control and next-generation intelligent edge systems. More details may be found on the product page and the press release.
